--
library ieee;
use ieee.std_logic_1164.all;

entity mux is 
port (
	
	r1,r2,r3,r4 : in std_logic_vector(31 downto 0);
	output : out std_logic_vector(31 downto 0);
	selec :in std_logic_vector(5 downto 0);
	 --clk			: in	  std_logic
	 ); 
     
end mux;     
        

architecture mux_behaviour of mux is
    signal  tmp_out : std_logic_vector(31 downto 0);
begin
    
process(clk)
              
begin  
	--if(clk = '1' and clk'event)	then
	
--	 	en esta parte va un caes con la seleccion del mux
--	 	    con los bit mas altos   
	
	
	--output <= tmp_out;
end process;

end mux_behaviour;





